library ieee;
use ieee.std_logic_1164.all;

entity alu_tb is
end alu_tb;

architecture behav of alu_tb is
    component alu
        port(
        a, b: in std_logic_vector(31 downto 0);
        alucontrol: in std_logic_vector(2 downto 0);
        result: out std_logic_vector(31 downto 0);
        zero: out std_logic
        );
    end component;

    signal a_s, b_s, result_s: std_logic_vector(31 downto 0);
    signal alucontrol_s: std_logic_vector(2 downto 0);
    signal zero_s: std_logic;

begin
    ALU0: alu port map(a_s, b_s, alucontrol_s, result_s, zero_s);
    process
    begin
    a_s <= x"00000010";
    b_s <= x"ffffffff";

    alucontrol_s <= "000"; -- a and b
    wait for 1 ns;
    assert result_s = x"00000010";
    assert zero_s = '0';

    alucontrol_s <= "001"; -- a or b
    wait for 1 ns;
    assert result_s = x"ffffffff";
    assert zero_s = '0';

    alucontrol_s <= "010"; -- a + b
    wait for 1 ns;
    assert result_s = x"0000000f";
    assert zero_s = '0';

    alucontrol_s <= "100"; -- a and not(b)
    wait for 1 ns;
    assert result_s = x"00000000";
    assert zero_s = '1';

    alucontrol_s <= "101"; -- a or not(b)
    wait for 1 ns;
    assert result_s = x"00000010";
    assert zero_s = '0';

    alucontrol_s <= "110"; -- a - b
    wait for 1 ns;
    assert result_s = x"00000011";
    assert zero_s = '0';

    alucontrol_s <= "111"; -- "1" if (a < b)
    wait for 1 ns;
    assert result_s = x"00000001";
    assert zero_s = '0';

    wait;
    end process;
end behav;
